Three-dimensional chip-multiprocessor run-time thermal management C Zhu, Z Gu, L Shang, RP Dick, R Joseph IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 241 | 2008 |
ISAC: Integrated space-and-time-adaptive chip-package thermal analysis Y Yang, Z Gu, C Zhu, RP Dick, L Shang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 176 | 2006 |
Sparse tensor core: Algorithm and hardware co-design for vector-wise sparse neural networks on modern gpus M Zhu, T Zhang, Z Gu, Y Xie Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 160 | 2019 |
Reliable multiprocessor system-on-chip synthesis C Zhu, Z Gu, RP Dick, L Shang Proceedings of the 5th IEEE/ACM international conference on Hardware …, 2007 | 73 | 2007 |
TAPHS: Thermal-aware unified physical-level and high-level synthesis Z Gu, Y Yang, J Wang, RP Dick, L Shang Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 69 | 2006 |
Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design Y Yang, C Zhu, Z Gu, L Shang, RP Dick Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 60 | 2006 |
Application-specific MPSoC reliability optimization Z Gu, C Zhu, L Shang, RP Dick IEEE transactions on very large scale integration (VLSI) systems 16 (5), 603-608, 2008 | 55 | 2008 |
Incremental exploration of the combined physical and behavioral design space Z Gu, J Wang, RP Dick, H Zhou Proceedings of the 42nd annual Design Automation Conference, 208-213, 2005 | 52 | 2005 |
Unified incremental physical-level and high-level synthesis Z Gu, J Wang, RP Dick, H Zhou IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 43 | 2007 |
Energon: Toward efficient acceleration of transformers using dynamic sparse attention Z Zhou, J Liu, Z Gu, G Sun IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 39 | 2022 |
Adaptive chip-package thermal analysis for synthesis and design Y Yang, Z Gu, C Zhu, L Shang, RP Dick Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 31 | 2006 |
Duet: Boosting deep neural network efficiency on dual-module architecture L Liu, Z Qu, L Deng, F Tu, S Li, X Hu, Z Gu, Y Ding, Y Xie 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 29 | 2020 |
Towards an ultra-low-power architecture using single-electron tunneling transistors C Zhu, Z Gu, L Shang, RP Dick, RG Knobel Proceedings of the 44th annual Design Automation Conference, 312-317, 2007 | 26 | 2007 |
Method and apparatus for generating push notifications Z Huasha, X Li, Q Zhang, SI Luo, Z Gu, Q Zhang US Patent 10,757,218, 2020 | 21 | 2020 |
Statistical formal activity analysis with consideration of temporal and spatial correlations Z Gu, KS McElvain US Patent 8,161,434, 2012 | 18 | 2012 |
Characterization of single-electron tunneling transistors for designing low-power embedded systems C Zhu, Z Gu, RP Dick, L Shang, RG Knobel IEEE transactions on very large scale integration (VLSI) systems 17 (5), 646-659, 2009 | 15 | 2009 |
Boosting deep neural network efficiency with dual-module inference L Liu, L Deng, Z Chen, Y Wang, S Li, J Zhang, Y Yang, Z Gu, Y Ding, ... International Conference on Machine Learning, 6205-6215, 2020 | 13 | 2020 |
Systems and methods for providing vector-wise sparsity in a neural network ZHU Maohua, T Zhang, Z Gu, Y Xie US Patent App. 16/937,202, 2021 | 11 | 2021 |
Functional verification methodology of a 32-bit risc microprocessor Z Gu, Z Yu, B Shen, Q Zhang IEEE 2002 International Conference on Communications, Circuits and Systems …, 2002 | 9 | 2002 |
Statistical formal activity analysis with consideration of temporal and spatial correlations Z Gu, KS McElvain US Patent 8,656,327, 2014 | 5 | 2014 |