| Germanium-on-insulator (GeOI) substrates—a novel engineered substrate for future high performance devices T Akatsu, C Deguet, L Sanchez, F Allibert, D Rouchon, T Signamarcheix, ... Materials science in semiconductor processing 9 (4-5), 444-448, 2006 | 181 | 2006 |
| High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond Q Liu, M Vinet, J Gimbert, N Loubet, R Wacquez, L Grenouillet, Y Le Tiec, ... Electron Devices Meeting (IEDM), 2013 IEEE International, 9.2.1-9.2.4, 2013 | 123 | 2013 |
| High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET K Cheng, A Khakifirooz, N Loubet, S Luning, T Nagumo, M Vinet, Q Liu, ... 2012 International Electron Devices Meeting, 18.1. 1-18.1. 4, 2012 | 121 | 2012 |
| Fabrication and characterisation of 200 mm germanium-on-insulator (GeOI) substrates made from bulk germanium C Deguet, L Sanchez, T Akatsu, F Allibert, J Dechamp, F Madeira, ... Electronics Letters 42 (7), 415-417, 2006 | 100 | 2006 |
| Manufacturing method for a semiconductor on insulator type substrate for radiofrequency applications F Allibert, J Widiez US Patent 9,129,800, 2015 | 86 | 2015 |
| Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization G Hamaide, F Allibert, H Hovel, S Cristoloveanu Journal of applied physics 101 (11), 114513, 2007 | 80 | 2007 |
| The multiple-gate MOS-JFET transistor BJ BLALOCK, S CRISTOLOVEANU, BM DUFRENE, F Allibert, ... International journal of high speed electronics and systems 12 (02), 511-520, 2002 | 79 | 2002 |
| Germanium-On-Insulator (GeOI) Structure Realized by the Smart Cut™ Technology F Letertre, C Deguet, C Richtarch, B Faure, JM Hartmann, F Chieu, ... MRS Proceedings 809, B4. 4, 2004 | 71 | 2004 |
| The four-gate transistor S Cristoloveanu, B Blalock, F Allibert, B Dufrene, M Mojarradi Solid-State Device Research Conference, 2002. Proceeding of the 32nd …, 2002 | 43 | 2002 |
| From SOI materials to innovative devices F Allibert, T Ernst, J Pretet, N Hefyene, C Perret, A Zaslavsky, ... Solid-State Electronics 45 (4), 559-566, 2001 | 43 | 2001 |
| Physical Models of Planar Spiral Inductor Integrated on the High-Resistivity and Trap-Rich Silicon-on-Insulator Substrates S Liu, L Zhu, F Allibert, I Radu, X Zhu, Y Lu IEEE Transactions on Electron Devices 64 (7), 2775-2781, 2017 | 39 | 2017 |
| FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node Q Liu, B DeSalvo, P Morin, N Loubet, S Pilorget, F Chafik, S Maitrejean, ... 2014 IEEE International Electron Devices Meeting, 9.1. 1-9.1. 4, 2014 | 38 | 2014 |
| A mobility enhancement strategy for sub-14nm power-efficient FDSOI technologies B DeSalvo, P Morin, M Pala, G Ghibaudo, O Rozeau, Q Liu, A Pofelski, ... 2014 IEEE International Electron Devices Meeting, 7.2. 1-7.2. 4, 2014 | 34 | 2014 |
| A SPDT RF switch small-and large-signal characteristics on TR-HR SOI substrates BK Esfeh, M Rack, S Makovejev, F Allibert, JP Raskin IEEE Journal of the Electron Devices Society 6, 543-550, 2018 | 33 | 2018 |
| A SPDT RF switch small-and large-signal characteristics on TR-HR SOI substrates B Kazemi Esfeh, S Makovejev, F Allibert, JP Raskin IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2017 | 33* | 2017 |
| Double-gate MOSFETs: Is gate alignment mandatory? F Allibert, A Zaslavsky, J Pretet, S Cristoloveanu 31st European Solid-State Device Research Conference, 267-270, 2001 | 31 | 2001 |
| Internal Dissolution of Buried Oxide in SOI Wafers O Kononchuk, F Boedt, F Allibert Solid State Phenomena 131, 113-118, 2008 | 30 | 2008 |
| Modeling of Semiconductor Substrates for RF Applications: Part I—Static and Dynamic Physics of Carriers and Traps M Rack, F Allibert, JP Raskin IEEE Transactions on Electron Devices 68 (9), 4598-4605, 2021 | 27 | 2021 |
| Transition from partial to full depletion in silicon-on-insulator transistors: Impact of channel length F Allibert, J Pretet, G Pananakakis, S Cristoloveanu Applied physics letters 84 (7), 1192-1194, 2004 | 26 | 2004 |
| Substrate having a charged zone in an insulating buried layer M Shaheen, F Allibert, G Gaudin, F Lallement, D Landru, K Landry, ... US Patent 8,535,996, 2013 | 24 | 2013 |
Cristoloveanu, SorinGrenoble INPVerified email at grenoble-inp.fr