| A 16-bit 4'th order noise-shaping D/A converter LR Carley, J Kenney Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation, 482, 1988 | 111 | 1988 |
| Design of multibit noise-shaping data converters JG Kenney, LR Carley Computer-Aided Design of Analog Circuits and Systems, 99-112, 1993 | 98 | 1993 |
| Multi-level decision feedback equalization for saturation recording JG Kenney, LR Carley, RW Wood IEEE transactions on magnetics 29 (4), 2160-2171, 1993 | 94 | 1993 |
| CLANS: A high-level synthesis tool for high resolution data converters JG Kenney, LR Carley 1988 IEEE International Conference on Computer-Aided Design, 496,497,498,499 …, 1988 | 61 | 1988 |
| Multi-level decision feedback equalization: An efficient realization of FDTS/DF JG Kenney, R Wood IEEE transactions on magnetics 31 (2), 1115-1120, 1995 | 51 | 1995 |
| Continuous-rate clock recovery circuit JG Kenney US Patent 8,509,371, 2013 | 31 | 2013 |
| An enhanced slew rate source follower JG Kenney, G Rangan, K Ramamurthy, G Temes IEEE journal of solid-state circuits 30 (2), 144-146, 1995 | 31 | 1995 |
| Frequency acquisition system JG Kenney, L DeVito US Patent 6,803,827, 2004 | 30 | 2004 |
| A 5.6 GHz to 11.5 GHz DCO for digital dual loop CDRs WS Titus, JG Kenney IEEE journal of solid-state circuits 47 (5), 1123-1130, 2012 | 29 | 2012 |
| Allpass forward equalizer for decision feedback equalization PA McEwen, JG Kenney IEEE transactions on magnetics 31 (6), 3045-3047, 1995 | 27 | 1995 |
| Comparison of computationally efficient forms of FDTS/DF against PR4-ML LR Carley, JG Kenney IEEE transactions on magnetics 27 (6), 4567-4572, 1991 | 27 | 1991 |
| A 9.95–11.3-Gb/s XFP Transceiver in 0.13- CMOS JG Kenney, D Dalton, E Evans, MH Eskiyerli, B Hilton, D Hitchcox, T Kwok, ... IEEE journal of solid-state circuits 41 (12), 2901-2910, 2006 | 23 | 2006 |
| Geometric representation of the tree-search detector JG Kenney, LR Carley [Conference Record] SUPERCOMM/ICC'92 Discovering a New World of …, 1992 | 21 | 1992 |
| Apparatus and methods for quadrature clock signal generation R Schell, J Kenney, WH Chen US Patent 8,760,209, 2014 | 20 | 2014 |
| A 15-Gb/s sub-baud-rate digital CDR D Kim, WS Choi, A Elkholy, J Kenney, PK Hanumolu IEEE Journal of Solid-State Circuits 54 (3), 685-695, 2019 | 18 | 2019 |
| Apparatus and methods for clock and data recovery S McCracken, J Kenney, K Tam US Patent 9,184,909, 2015 | 18 | 2015 |
| LC tank clock driver with automatic tuning JG Kenney Jr, V Reddy, WS Titus US Patent 7,126,403, 2006 | 17 | 2006 |
| Apparatus and method for clock and data recovery J Kenney US Patent 8,442,173, 2013 | 15 | 2013 |
| A comparative study of two adaptive continuous-time filters for decision feedback equalization read channels NDF Garrido, JE Franca, JG Kenney 1997 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 89-92, 1997 | 15 | 1997 |
| Method of static phase offset correction for a linear phase detector J Kenney, JZ Walker US Patent 8,948,332, 2015 | 14 | 2015 |
