| High voltage generation and regulation system for digital multilevel nonvolatile memory WJ Saiki, H Van Tran, SM Khan US Patent 6,867,638, 2005 | 251 | 2005 |
| Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system H Van Tran, SM Khan, GJ Korsh US Patent 6,282,145, 2001 | 140 | 2001 |
| Multistage autozero sensing for a multilevel non-volatile memory integrated circuit system H Van Tran US Patent 6,956,779, 2005 | 125 | 2005 |
| Digital multilevel memory system having multistage autozero sensing H Van Tran US Patent 7,031,214, 2006 | 123 | 2006 |
| Testing of multilevel semiconductor memory GJ Korsh, SM Khan, H Van Tran US Patent 6,396,742, 2002 | 115 | 2002 |
| Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features H Van Tran, S Saha US Patent 8,385,147, 2013 | 114 | 2013 |
| Deep Learning Neural Network Classifier Using Non-volatile Memory Array FM Bayat, X Guo, D Strukov, N Do, H Van Tran, V Tiwari, M Reiten US Patent App. 15/594,439, 2017 | 109* | 2017 |
| Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system H Van Tran, SM Khan, GJ Korsh US Patent 6,519,180, 2003 | 108 | 2003 |
| Digital multilevel non-volatile memory system H Van Tran US Patent 6,975,539, 2005 | 106 | 2005 |
| Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory H Van Tran, SM Khan US Patent 7,471,581, 2008 | 88 | 2008 |
| Method and apparatus for analog reading values stored in floating gate structures H Van Tran, J Brennan Jr, T Blyth, S Yoon US Patent 5,726,934, 1998 | 79 | 1998 |
| Unified multilevel cell memory H Van Tran, HQ Nguyen, V Sarin, LB Hoang, I Nojima US Patent 7,019,998, 2006 | 72 | 2006 |
| Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system H Van Tran, HQ Nguyen, A Levi, I Nojima US Patent 7,149,110, 2006 | 71 | 2006 |
| Differential sense amplifier for multilevel non-volatile memory H Van Tran, JE Frayer, WJ Saiki, MS Briner US Patent 6,885,600, 2005 | 63 | 2005 |
| Integrated flash memory systems and methods for load compensation H Van Tran US Patent 7,660,161, 2010 | 60 | 2010 |
| MOS charge pump generation and regulation method and apparatus H Van Tran US Patent 5,808,506, 1998 | 58 | 1998 |
| High voltage shunt regulator for flash memory H Van Tran, TT Vu, S Karmakar US Patent 7,116,088, 2006 | 56 | 2006 |
| A 2.5 V 256-level non-volatile analog storage device using EEPROM technology H Van Tran, T Blyth, D Sowards, L Engh, BS Nataraj, T Dunne, H Wang, ... 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical …, 1996 | 56 | 1996 |
| Method and apparatus of column redundancy for non-volatile analog and multilevel memory H Van Tran, J Brennan Jr US Patent 6,002,620, 1999 | 54 | 1999 |
| Sensing circuit with sampled reference current or voltage for flash memory system H Van Tran, A Ly, T Vu, HQ Nguyen, VT Nguyen US Patent 10,141,062, 2018 | 53* | 2018 |
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