| Design and analysis of different types SRAM cell topologies PNV Kiran, N Saxena 2015 2nd International Conference on Electronics and Communication Systems …, 2015 | 42 | 2015 |
| Leakage current reduction in CMOS circuits using stacking effect N Saxena, S Soni International Journal of Application or Innovation in Engineering …, 2013 | 20 | 2013 |
| Design of an amplifier through second generation current conveyor N Tripathi, N Saxena, S Soni arXiv preprint arXiv:1402.2230, 2014 | 11 | 2014 |
| Low power design and simulation of 7T SRAM cell using various circuit techniques P Agarwal, N Saxena, N Tripathi International Journal of Engineering Trends and Technology (IJETT …, 2013 | 10 | 2013 |
| Reduction of leakage power & noise for DRAM design using sleep transistor technique P Kushwah, N Saxena, S Akashe 2015 Fifth International Conference on Advanced Computing & Communication …, 2015 | 8 | 2015 |
| Design of a power efficient D-flip flop using AVL technique S Gupta, N Saxena European Journal of Advances in Engineering and Technology 2 (12), 75-78, 2015 | 6 | 2015 |
| Parameter Analysis of Different SRAM Cell Topologies and Design of 10SRAM Cell at 45nm Technology with Improved Read Speed NS PN Vamsi Kiran International conference on emerging trends in computer science & its …, 2015 | 6* | 2015 |
| SRTLock: A sensitivity resilient two-tier logic encryption scheme N Saxena, RV Narayanan, JK Meka, R Vemuri 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 389-394, 2021 | 4 | 2021 |
| A Darlington Pair Based CMOS Two Stage Operational Amplifier at 32nm Technology V Yadav, N Saxena, A Rajput International Journal of Engineering Trends and Technology 43 (1), 53-57, 2017 | 4 | 2017 |
| ISPLock: A hybrid internal state locking method using polymorphic gates N Saxena, R Vemuri 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 140-145, 2022 | 3 | 2022 |
| Efficient and High-Performance MTCMOS Employed 34T-Full Subtractor. A Sharma, N Saxena, AS Rajput Journal of Active & Passive Electronic Devices 13 (1), 2018 | 3 | 2018 |
| Technique to reduce papr problem in next-generation wireless communication system A Kumar, V Mishra, S Tyagi, P Saini, N Saxena Architectural Wireless Networks Solutions and Security Issues, 283-300, 2021 | 2 | 2021 |
| An analysis of novel 12T SRAM cell with ımproved read stability G Upadhyay, AS Rajput, N Saxena Int. J. Innov. Res. Eng. Appl. Sci 3 (310717), 3, 2017 | 2 | 2017 |
| Analysis of Different SRAM Cell Topologies and Design of 10T SRAM Cell with Improved Read Speed. N SAXENA, S SONI Journal of Active & Passive Electronic Devices 11 (1), 2016 | 2 | 2016 |
| Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption N Saxena, R Vemuri 2023 IEEE 66th International Midwest Symposium on Circuits and Systems …, 2024 | 1 | 2024 |
| Enhancing Output Corruption Through GSHE Switch Based Logic Encryption N Saxena, R Vemuri 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024 | 1 | 2024 |
| Design and Analysis of Cascode Amplifier with Improved Gain N Saxena, P Agarwal, S Soni Journal of Computational and Theoretical Nanoscience 14 (11), 5654-5656, 2017 | 1 | 2017 |
| Analysis of Read-Stability and Write-Ability FinFET SRAM Cells AK Sharma, N Saxena International Journal of Engineering Trends and Technology (IJETT) 44 (1), 51-53, 2017 | 1 | 2017 |
| Improvement in read performance of 10T SRAM cell using body biasing in forward bias regime R Gupta, AS Rajput, N Saxena IPASJ Int. J. Electron. Commun 4, 1-9, 2016 | 1 | 2016 |
| Tolerant design of low power D Flip Flop using GDI and DSTC for higher performance S Gupta, N Saxena 2015 International Conference on Communication Networks (ICCN), 339-342, 2015 | 1 | 2015 |
Dr Amit Singh Rajputchhattisgarh swami vivekanand technical universityVerified email at csvtu.ac.in
