Chun-Cheng (Jason) Liu

Chun-Cheng (Jason) Liu

Principal Engineer, NVIDIA
Verified email at nvidia.com
Cited by 3856
ADC DAC Analog Filter Serdes Wireline
José A Tierno

José A Tierno

Scientist, Apple Inc.
Verified email at apple.com
Cited by 3610
Digital design Mixed signal design SerDes Digital PLLs Self-timed design
Timothy (Tod) Dickson

Timothy (Tod) Dickson

Principal Research Scientist, IBM TJ Watson Research Center
Verified email at us.ibm.com
Cited by 2876
High-speed integrated circuits I/O SERDES
Kostas Pagiamtzis

Kostas Pagiamtzis

Principal, Convex IC Inc.
Verified email at convexic.com
Cited by 2140
SerDes CTLE DFE CAM SRAM
Amir Amirkhany

Amir Amirkhany

Head of Samsung Display America Lab
Verified email at stanfordalumni.org
Cited by 1570
High-speed interfaces memory interface SERDES Display compensation Display driving
Chun-Ming Hsu

Chun-Ming Hsu

Intel
Verified email at intel.com
Cited by 1432
PLL Serdes RF ...
Taeksang Song

Taeksang Song

Samsung Electronics
Verified email at samsung.com
Cited by 1197
SoC memory controller NVM SerDes RF
Davide TONIETTO

Davide TONIETTO

Fellow, Director of Engineering, Huawei Canada
Verified email at huawei.com
Cited by 1179
IC design analog design wireline communication SerDes
Ariel Cohen

Ariel Cohen

Sr. Principal Engineer, mixed signal Serdes design at Intel
Verified email at intel.com
Cited by 927
SERDES analog circuits ADCs thermal sensors biosensors and neuroelectronic hybrids
Mike Peng Li

Mike Peng Li

Fellow, Intel Corporation
Verified email at intel.com
Cited by 878
SERDES transceiver high-speed I/Os interconnect jitter
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