Profiles

Dhiraj K Pradhan

Professor of Computer Science, University of Bristol

Verified email at cs.bris.ac.uk

Cited by 15127

Fault tolerance Logic Synthesis Computer architecture error correcting codes Galois Field

Marek Perkowski

Professor of Electrical and Computer Engineering, Portland State University

Verified email at pdx.edu

Cited by 9567

multiple-valued logic reversible logic logic synthesis quantum computing

Niklas Een

Researcher at Google

Verified email at een.se

Cited by 9434

Machine Learning Formal verification Logic synthesis

Tsutomu Sasao

Visiting Professor, Meiji University

Verified email at cs.meiji.ac.jp

Cited by 9139

Logic synthesis Multiple-valued logic Logic Design Switching Theory

Alexander Barkalov

Professor, University of Zielona Góra

Verified email at iie.uz.zgora.pl

Cited by 6467

Logic Synthesis Control Units VLSI

Mathias Soeken

Microsoft

Verified email at epfl.ch

Cited by 5519

Computer Science Logic Synthesis Quantum Computing

Gerhard W Dueck

Professor of Computer Science, University of New Brunswick

Verified email at unb.ca

Cited by 5357

Logic Synthesis Reversible Logic Garbage Collection

Marc Riedel

Full Professor of Electrical and Computer Engineering, University of Minnesota

Verified email at umn.edu

Cited by 4838

Logic Synthesis Logic Verification Formal Verification Synthetic Biology Molecular Computing

Fabrizio Ferrandi

Politecnico di Milano

Verified email at polimi.it

Cited by 4030

High-Level Synthesis HW/SW codesign Reconfigurable Computing Logic synthesis Embedded Systems

Maciej Ciesielski

Professor of ELectrical and Computer Engineering

Verified email at ecs.umass.edu

Cited by 3641

Formal verification SImulation Logic synthesis High-level Synthesis

1 - 10