Παρακολούθηση
Nuno Lourenço
Nuno Lourenço
Instituto de Telecomunicações (IT), Instituto Superior Técnico - Universidade de Lisboa
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα lx.it.pt - Αρχική σελίδα
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Παρατίθεται από
Παρατίθεται από
Έτος
LAYGEN II—Automatic layout generation of analog integrated circuits
R Martins, N Lourenco, N Horta
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
1162013
Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
E Afacan, N Lourenço, R Martins, G Dündar
Integration 77, 113-130, 2021
1052021
Using artificial neural networks for analog integrated circuit design automation
JPS Rosa, DJD Guerra, NCG Horta, FM Martins, NCC Lourenço
Springer, 2020
71*2020
GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation
N Lourenço, N Horta
Proceedings of the 14th annual conference on Genetic and evolutionary …, 2012
712012
Network core access architecture
JT De Sousa, NCC Lourenco, NGDR Ribeiro, VMG Martins, RJS Martins
US Patent 8,019,832, 2011
582011
AIDA:Layout-aware analog circuit level sizing with in-loop layout generation
N Lourenço, R Martins, A Canelas, R Póvoa, N Horta
Integration, the VLSI Journal, 2016
57*2016
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction
N Lourenço, R Martins, N Horta
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
542015
AIDA: Automated analog IC design flow from circuit level to layout
R Martins, N Lourenço, S Rodrigues, J Guilherme, N Horta
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
512012
Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
N Lourenço, R Martins, N Horta
Springer International Publishing, 2017
482017
Laygen-automatic layout generation of analog ics from hierarchical template descriptions
N Lourenço, M Vianello, J Guilherme, N Horta
2006 Ph. D. Research in Microelectronics and Electronics, 213-216, 2006
442006
On the exploration of promising analog ic designs via artificial neural networks
N Lourenço, J Rosa, R Martins, H Aidos, A Canelas, R Póvoa, N Horta
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
432018
Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates
R Martins, N Lourenço, N Horta
Expert Systems with Applications 42 (23), 9137-9151, 2015
412015
AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation
R Martins, N Lourenço, A Canelas, R Póvoa, N Horta
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
412015
Many-objective sizing optimization of a class-C/D VCO for ultralow-power IoT and ultralow-phase-noise cellular applications
R Martins, N Lourenço, N Horta, J Yin, PI Mak, RP Martins
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 69-82, 2018
402018
Two-step RF IC block synthesis with preoptimized inductors and full layout generation in-the-loop
R Martins, N Lourenço, F Passos, R Póvoa, A Canelas, E Roca, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
392018
Using polynomial regression and artificial neural networks for reusable analog IC sizing
N Lourenço, E Afacan, R Martins, F Passos, A Canelas, R Póvoa, N Horta, ...
2019 16th International Conference on Synthesis, Modeling, Analysis and …, 2019
382019
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques
R Povoa, I Bastos, N Lourenço, N Horta
Integration 52, 243-252, 2016
382016
Floorplan-aware analog IC sizing and optimization based on topological constraints
N Lourenço, A Canelas, R Póvoa, R Martins, N Horta
Integration 48, 183-197, 2015
382015
Design of a 4.2-to-5.1 GHz ultralow-power complementary class-B/C hybrid-mode VCO in 65-nm CMOS fully supported by EDA tools
R Martins, N Lourenço, N Horta, S Zhong, J Yin, PI Mak, RP Martins
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3965-3977, 2020
332020
FUZYE: A Fuzzy -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms
A Canelas, R Póvoa, R Martins, N Lourenço, J Guilherme, JP Carvalho, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
332018
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