| Biochipwork: Reverse engineering of microfluidic biochips H Chen, S Potluri, F Koushanfar 2017 IEEE International Conference on Computer Design (ICCD), 9-16, 2017 | 47 | 2017 |
| Machine learning and hardware security: Challenges and opportunities F Regazzoni, S Bhasin, AA Pour, I Alshaer, F Aydin, A Aysu, V Beroulle, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-6, 2020 | 30 | 2020 |
| SeqL: Secure Scan-Locking for IP Protection S Potluri, A Aysu, A Kumar 2020 21st International Symposium on Quality Electronic Design (ISQED), 7-13, 2020 | 30* | 2020 |
| 2Deep: Enhancing side-channel attacks on lattice-based key-exchange via 2-D Deep Learning P Kashyap, F Aydin, S Potluri, PD Franzon, A Aysu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 23 | 2020 |
| Architecture synthesis for cost-constrained fault-tolerant flow-based biochips MC Eskesen, P Pop, S Potluri 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 618-623, 2016 | 17 | 2016 |
| iTimed: Cache attacks on the Apple A10 Fusion SoC G Haas, S Potluri, A Aysu 2021 IEEE International Symposium on Hardware Oriented Security and Trust …, 2021 | 16 | 2021 |
| RevEAL: Single-trace side-channel leakage of the SEAL homomorphic encryption library F Aydin, E Karabulut, S Potluri, E Alkim, A Aysu 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022 | 15 | 2022 |
| Design-for-testability of on-chip control in mVLSI biochips S Potluri, P Pop, J Madsen IEEE Design & Test 36 (1), 48-56, 2018 | 12 | 2018 |
| DFT assisted techniques for peak launch-to-capture power reduction during launch-on-shift at-speed testing S Potluri, AS Trinadh, SB Ch, V Kamakoti, N Chandrachoodan ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (1 …, 2015 | 12 | 2015 |
| DeePar-SCA: Breaking parallel architectures of lattice cryptography via learning based side-channel attacks F Aydin, P Kashyap, S Potluri, P Franzon, A Aysu Embedded Computer Systems: Architectures, Modeling, and Simulation: 20th …, 2020 | 11 | 2020 |
| Security of microfluidic biochip: Practical attacks and countermeasures H Chen, S Potluri, F Koushanfar ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (3 …, 2020 | 9 | 2020 |
| Towards ai-enabled hardware security: Challenges and opportunities H Sayadi, M Aliasgari, F Aydin, S Potluri, A Aysu, J Edmonds, ... 2022 IEEE 28th International Symposium on On-Line Testing and Robust System …, 2022 | 8 | 2022 |
| MLTimer: Leakage power minimization in digital circuits using machine learning and adaptive lazy timing analysis S Patanjali, M Patnaik, S Potluri, V Kamakoti Journal of Low Power Electronics 14 (2), 285-301, 2018 | 8 | 2018 |
| Stealing neural network models through the scan chain: A new threat for ML hardware S Potluri, A Aysu 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-8, 2021 | 7 | 2021 |
| XStat: Statistical X-filling algorithm for peak capture power reduction in scan tests AS Trinadh, S Potluri, S Balachandran, CS Babu, V Kamakoti Journal of Low Power Electronics 10 (1), 107-115, 2014 | 7 | 2014 |
| Efficacy of satisfiability-based attacks in the presence of circuit reverse-engineering errors Q Tan, S Potluri, A Aysu 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 5 | 2020 |
| Flowtrojan: Insertion and detection of hardware trojans on flow-based microfluidic biochips H Chen, S Potluri, F Koushanfar 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS …, 2020 | 5 | 2020 |
| A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips V Gokulkrishnan, V Kamakoti, N Chandrachoodan, S Potluri 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2017 | 4 | 2017 |
| Optimal don’t care filling for minimizing peak toggles during at-speed stuck-at testing AS Trinadh, S Potluri, SB Ch, V Kamakoti, SG Singh ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (1 …, 2017 | 4 | 2017 |
| Synthesis of on-chip control circuits for mVLSI biochips S Potluri, A Schneider, P Pop, J Madsen Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 4 | 2017 |
