| A reconfigurable fabric for accelerating large-scale datacenter services A Putnam, AM Caulfield, ES Chung, D Chiou, K Constantinides, J Demme, ... ACM SIGARCH Computer Architecture News 42 (3), 13-24, 2014 | 1574 | 2014 |
| Scaling to the End of Silicon with EDGE Architectures D Burger, SW Keckler, KS McKinley, M Dahlin, LK John, C Lin, CR Moore, ... Computer 37 (7), 44-55, 2004 | 546 | 2004 |
| Evaluating and optimizing OpenCL kernels for high performance computing with FPGAs HR Zohouri, N Maruyama, A Smith, M Matsuda, S Matsuoka SC'16: Proceedings of the International Conference for High Performance …, 2016 | 225 | 2016 |
| A reconfigurable fabric for accelerating large-scale datacenter services A Putnam, AM Caulfield, ES Chung, D Chiou, K Constantinides, J Demme, ... IEEE Micro 35 (3), 10-22, 2015 | 178 | 2015 |
| Compiling for EDGE architectures A Smith, J Burrill, J Gibson, B Maher, N Nethercote, B Yoder, D Burger, ... International Symposium on Code Generation and Optimization (CGO'06), 11 pp.-195, 2006 | 158 | 2006 |
| An evaluation of the TRIPS computer system M Gebhart, BA Maher, KE Coons, J Diamond, P Gratz, M Marino, ... ACM SIGARCH Computer Architecture News 37 (1), 1-12, 2009 | 92 | 2009 |
| Hybrid block-based processor and custom function blocks AL Smith, JS Gray US Patent 11,449,342, 2022 | 63 | 2022 |
| A reconfigurable fabric for accelerating large-scale datacenter services A Putnam, AM Caulfield, ES Chung, D Chiou, K Constantinides, J Demme, ... Communications of the ACM 59 (11), 114-122, 2016 | 56 | 2016 |
| Energy efficient multi-modal instruction issue DC Burger, AL Smith US Patent 9,547,496, 2017 | 49 | 2017 |
| Dataflow predication A Smith, R Nagarajan, K Sankaralingam, R McDonald, D Burger, ... 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006 | 48 | 2006 |
| Raising binaries to llvm ir with mctoll (wip paper) SB Yadavalli, A Smith Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on …, 2019 | 43 | 2019 |
| Prefetching associated with predicated load instructions DC Burger, AL Smith US Patent App. 15/061,370, 2017 | 41 | 2017 |
| Block-based processor core composition register DC Burger, AL Smith US Patent 11,126,433, 2021 | 37 | 2021 |
| Configuring modes of processor operation DC Burger, AL Smith US Patent App. 14/757,944, 2017 | 32 | 2017 |
| Merging head and tail duplication for convergent hyperblock formation BA Maher, A Smith, D Burger, KS McKinley 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006 | 32 | 2006 |
| Large-scale reconfigurable computing in a microsoft datacenter A Putnam, A Caulfield, E Chung, D Chiou, K Constantinides, J Demme, ... 2014 IEEE Hot Chips 26 Symposium (HCS), 1-38, 2014 | 28 | 2014 |
| Block-based processor including topology and control registers to indicate resource sharing and size of logical processor DC Burger, AL Smith US Patent 10,768,936, 2020 | 25 | 2020 |
| A machine learning approach to mapping streaming workloads to dynamic multicore processors PJ Micolet, A Smith, C Dubach Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages …, 2016 | 24 | 2016 |
| Broadcast channel architectures for block-based processors DC Burger, AL Smith US Patent 10,452,399, 2019 | 23 | 2019 |
| Age-based management of instruction blocks in a processor instruction window DC Burger, A Smith, J Gray US Patent 9,946,548, 2018 | 23 | 2018 |
