| Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications T Francois, L Grenouillet, J Coignus, P Blaise, C Carabasse, N Vaxelaire, ... 2019 IEEE International Electron Devices Meeting (IEDM), 15.7. 1-15.7. 4, 2019 | 120 | 2019 |
| Impact of area scaling on the ferroelectric properties of back-end of line compatible Hf0.5Zr0.5O2 and Si:HfO2-based MFM capacitors T Francois, L Grenouillet, J Coignus, N Vaxelaire, C Carabasse, ... Applied Physics Letters 118 (6), 062904, 2021 | 32 | 2021 |
| 16kbit HfO2:Si-based 1T-1C FeRAM Arrays Demonstrating High Performance Operation and Solder Reflow Compatibility T Francois, J Coignus, A Makosiej, B Giraud, C Carabasse, J Barbot, ... 2021 IEEE International Electron Devices Meeting (IEDM), 33.1. 1-33.1. 4, 2021 | 29 | 2021 |
| High-Performance Operation and Solder Reflow Compatibility in BEOL-Integrated 16-Kb HfO₂: Si-Based 1T-1C FeRAM Arrays T Francois, J Coignus, A Makosiej, B Giraud, C Carabasse, J Barbot, ... IEEE Transactions on Electron Devices, 2022 | 19 | 2022 |
| Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations M Chambonneau, S Souiki-Figuigui, P Chiquet, V Della Marca, ... Applied Physics Letters 110 (16), 161112, 2017 | 8 | 2017 |
| Ferroelectric HfO2 for Memory Applications: Impact of Si Doping Technique and Bias Pulse Engineering on Switching Performance T Francois, J Coignus, L Grenouillet, JP Barnes, N Vaxelaire, J Ferrand, ... 2019 IEEE 11th International Memory Workshop (IMW) 66 (5), 1-4, 2019 | 7 | 2019 |
| Data retention under gate stress on a NVM array R Djenadi, G Micolau, J Postel-Pellerin, P Chiquet, R Laffont, JL Ogier, ... Solid-state electronics 78, 80-86, 2012 | 7 | 2012 |
| Charge loss activation during non-volatiles memory data retention J Postel-Pellerin, G Micolau, P Chiquet, R Laffont, F Lalande, JL Ogier CAS 2012 (International Semiconductor Conference) 2, 377-380, 2012 | 5 | 2012 |
| Phenomenological modelling of non-volatile memory threshold voltage shift induced by nonlinear ionization with a femtosecond laser P Chiquet, M Chambonneau, V Della Marca, J Postel-Pellerin, P Canet, ... Scientific reports 9 (1), 1-10, 2019 | 4 | 2019 |
| Simulation of the programming efficiency and the energy consumption of Flash memories during endurance degradation J Postel-Pellerin, P Chiquet, V Della Marca 2016 International Semiconductor Conference (CAS), 101-104, 2016 | 4 | 2016 |
| NVM cell degradation induced by femtosecond laser backside irradiation for reliability tests V Della Marca, M Chambonneau, S Souiki-Figuigui, J Postel-Pellerin, ... 2016 IEEE International Reliability Physics Symposium (IRPS), 7B-4-1-7B-4-7, 2016 | 4 | 2016 |
| Setting up of a floating gate test bench in a low noise environment to measure very low tunneling currents J Postel-Pellerin, G Micolau, P Chiquet, J Melkonian, G Just, D Boyer, ... Acta Imeko 4 (3), 36-41, 2015 | 4 | 2015 |
| All regimes mobility extraction using split C–V technique enhanced with charge-sheet model Q Hubert, M Carmona, B Rebuffat, J Innocenti, P Masson, L Masoero, ... Solid-State Electronics 111, 52-57, 2015 | 4 | 2015 |
| Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction V Della Marca, J Postel-Pellerin, T Kempf, A Régnier, P Chiquet, ... Microelectronics Reliability 88, 159-163, 2018 | 3 | 2018 |
| Experimental setup for non-destructive measurement of tunneling currents in semiconductor devices P Chiquet, P Masson, J Postel-Pellerin, R Laffont, G Micolau, F Lalande, ... Measurement 54, 234-240, 2014 | 3 | 2014 |
| Investigation of the effects of constant voltage stress on thin SiO2 layers using dynamic measurement protocols P Chiquet, P Masson, R Laffont, G Micolau, J Postel-Pellerin, F Lalande, ... Microelectronics Reliability 52 (9-10), 1895-1900, 2012 | 3 | 2012 |
| Robustness of the floating-gate technique in a very low-noise environment J Postel-Pellerin, G Micolau, C Abbas, P Chiquet, A Cavaillou 2014 International Semiconductor Conference (CAS), 287-290, 2014 | 2 | 2014 |
| Effect of Short Pulsed Program/Erase Cycling on Flash Memory Devices P Chiquet, J Postel-Pellerin, C Tuninetti, S Souiki-Figuigui, P Masson Proceedings of 14th IMEKO TC10 Workshop on Technical Diagnostics, Milan …, 2016 | 1 | 2016 |
| Improving Flash memory endurance and consumption with ultra-short channel-hot-electron programming pulses J Postel-Pellerin, P Chiquet, V Della Marca, T Wakrim, G Just, JL Ogier 2014 International Semiconductor Conference (CAS), 197-200, 2014 | 1 | 2014 |
| Very low tunneling current measurements using the Floating-Gate technique in a very low-noise environment J Postel-Pellerin, G Micolau, P Chiquet, J Melkonian, G Just, D Boyer, ... Proceedings of IMEKO TC4 Symposium, Benevento (Italy), 2014 | 1 | 2014 |
