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John Reuben
John Reuben
Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany
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Titel
Zitiert von
Zitiert von
Jahr
Memristive logic: A framework for evaluation and comparison
J Reuben, R Ben-Hur, N Wald, N Talati, AH Ali, PE Gaillardon, ...
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
862017
A modeling methodology for resistive ram based on stanford-pku model with extended multilevel capability
J Reuben, D Fey, C Wenger
IEEE transactions on nanotechnology 18, 647-656, 2019
582019
mmpu—a real processing-in-memory architecture to combat the von neumann bottleneck
N Talati, R Ben-Hur, N Wald, A Haj-Ali, J Reuben, S Kvatinsky
Applications of Emerging Memory Technology: Beyond Storage, 191-213, 2020
502020
Toward reliable compact modeling of multilevel 1T-1R RRAM devices for neuromorphic systems
E Perez-Bosch Quesada, R Romero-Zaliz, E Perez, ...
Electronics 10 (6), 645, 2021
462021
Incorporating variability of resistive RAM in circuit simulations using the Stanford–PKU model
J Reuben, M Biglari, D Fey
IEEE Transactions on Nanotechnology 19, 508-518, 2020
402020
Accelerated addition in resistive RAM array using parallel-friendly majority gates
J Reuben, S Pechmann
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (6 …, 2021
372021
Rediscovering majority logic in the post-CMOS era: A perspective from in-memory computing
J Reuben
Journal of low power Electronics and Applications 10 (3), 28, 2020
342020
Binary addition in resistance switching memory array by sensing majority
J Reuben
Micromachines 11 (5), 496, 2020
232020
A novel in-memory wallace tree multiplier architecture using majority logic
V Lakshmi, J Reuben, V Pudi
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (3), 1148-1158, 2021
222021
A time-based sensing scheme for multi-level cell (mlc) resistive ram
J Reuben, D Fey
2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and …, 2019
192019
A parallel-friendly majority gate to accelerate in-memory computation
J Reuben, S Pechmann
2020 IEEE 31st International Conference on Application-specific Systems …, 2020
132020
A taxonomy and evaluation framework for memristive logic
J Reuben, N Talati, N Wald, R Ben-Hur, AH Ali, PE Gaillardon, ...
Handbook of Memristor Networks, 1065-1099, 2019
112019
Capacitance driven clock mesh synthesis to minimize skew and power dissipation
J Reuben, S Nashit, HM Kittur
IEICE Electronics Express 10 (24), 20130850-20130850, 2013
112013
A novel clock generation algorithm for system-on-chip based on least common multiple
J Reuben, HM Kittur, M Shoaib
Computers & Electrical Engineering 40 (7), 2113-2125, 2014
102014
Low power, high speed hybrid clock divider circuit
J Reuben, ZV Mohammed, HM Kittur
2013 International Conference on Circuits, Power and Computing Technologies …, 2013
102013
Direct state transfer in MLC based memristive ReRAM devices for ternary computing
D Fey, J Reuben
2020 European Conference on Circuit Theory and Design (ECCTD), 1-5, 2020
92020
A buffer placement algorithm to overcome short-circuit power dissipation in mesh based clock distribution network
J Reuben, M Zackriya, HM Kittur, M Shoaib
Engineering Science and Technology, an International Journal 18 (2), 135-140, 2015
82015
Design of in-memory parallel-prefix adders
J Reuben
Journal of Low Power Electronics and Applications 11 (4), 45, 2021
62021
Clock frequency doubler circuit for multiple frequencies and its application in a CDN to reduce power
J Reuben, A Anuroop, HM Kittur
2012 International Conference on Computing, Electronics and Electrical …, 2012
62012
Minimal buffer insertion based low power clock tree synthesis for 3D integrated circuits
K Sumanth Kumar, J Reuben
Journal of Circuits, Systems and computers 25 (11), 1650142, 2016
52016
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