| LSOracle: A logic synthesis framework driven by artificial intelligence WL Neto, M Austin, S Temple, L Amaru, X Tang, PE Gaillardon 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2019 | 88* | 2019 |
| Logic synthesis meets machine learning: Trading exactness for generalization S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 40 | 2021 |
| Read your circuit: leveraging word embedding to guide logic optimization WL Neto, MT Moreira, L Amaru, C Yu, PE Gaillardon Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 26 | 2021 |
| SLAP: A supervised learning approach for priority cuts technology mapping WL Neto, MT Moreira, Y Li, L Amarù, C Yu, PE Gaillardon 2021 58th ACM/IEEE Design Automation Conference (DAC), 859-864, 2021 | 23 | 2021 |
| Flowtune: End-to-end automatic logic optimization exploration via domain-specific multiarmed bandit WL Neto, Y Li, PE Gaillardon, C Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 22 | 2022 |
| Logic synthesis meets machine learning: Trading exactness for generalization. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ... IEEE, 1026ś1031, 2021 | 11 | 2021 |
| A two-level approximate logic synthesis combining cube insertion and removal G Ammes, WL Neto, P Butzen, PE Gaillardon, RP Ribas IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 7 | 2022 |
| A scalable mixed synthesis framework for heterogeneous networks M Austin, S Temple, WL Neto, L Amarù, X Tang, PE Gaillardon 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 670-673, 2020 | 6 | 2020 |
| Improving LUT-based optimization for ASICs WL Neto, L Amarú, V Possani, P Vuillod, J Luo, A Mishchenko, ... Proceedings of the 59th ACM/IEEE Design Automation Conference, 421-426, 2022 | 5 | 2022 |
| Exact benchmark circuits for logic synthesis WL Neto, VN Possani, FS Marranghello, JM Matos, PE Gaillardon, AI Reis, ... IEEE Design & Test 37 (3), 51-58, 2019 | 5 | 2019 |
| Sleep convention logic isochronic fork: An analysis RA Guazzelli, MT Moreira, WL Neto, NLV Calazans Proceedings of the 30th Symposium on Integrated Circuits and Systems Design …, 2017 | 4 | 2017 |
| A standard cell characterization flow for non-standard voltage supplies M Gibiluka, MT Moreira, WL Neto, NLV Calazans 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2016 | 3 | 2016 |
| Improving logic optimization in sequential circuits using majority-inverter graphs WL Neto, X Tang, M Austin, L Amaru, PE Gaillardon 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 224-229, 2019 | 2 | 2019 |
| Lsoracle: Using mixed logic synthesis in an open source asic design flow S Temple, WL Neto, M Austin, X Tang, PE Gaillardon Workshop on Open-Source EDA Technology, 2021 | 1 | 2021 |
| Scalable Sequential Optimization Under Observability Don't Cares DS Marakkalage, E Testa, WL Neto, A Mishchenko, G De Micheli, ... 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024 | | 2024 |
| Getting the Most out of your Circuits with Heterogeneous Logic Synthesis S Temple, WL Neto, A Snelgrove, X Tang, PE Gaillardon 2021 58th ACM/IEEE Design Automation Conference (DAC), 1331-1334, 2021 | | 2021 |
| Exact multi-level benchmark circuit generation for logic synthesis evaluation WL Neto, VN Possani, FS Marranghello, JM Matos, AI Reis, RP Ribas 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2018 | | 2018 |
Pierre - Emmanuel GAILLARDONProfessor, University of Utahبريد إلكتروني تم التحقق منه على utah.edu
