| Ultra low voltage CMOS gates Y Berg, O Mirmotahari, PA Norseng, S Aunet 2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006 | 37 | 2006 |
| High speed ultra low voltage CMOS inverter Y Berg, O Mirmotahari, JG Lomsdalen, S Aunet 2008 IEEE Computer Society Annual Symposium on VLSI, 122-127, 2008 | 33 | 2008 |
| Pseudo floating-gate inverter with feedback control Y Berg, O Mirmotahari, S Aunet 2006 IFIP International Conference on Very Large Scale Integration, 272-277, 2006 | 26 | 2006 |
| On the design of new low-power CMOS standard ternary logic gates A Doostaregan, MH Moaiyeri, K Navi, O Hashemipour 2010 15th CSI International Symposium on Computer Architecture and Digital …, 2010 | 23 | 2010 |
| Pareto optimal based evolutionary approach for solving multi-objective facility layout problem KSN Ripon, K Glette, O Mirmotahari, M Høvin, J Tørresen Neural Information Processing: 16th International Conference, ICONIP 2009 …, 2009 | 22 | 2009 |
| A novel D-latch in multiple-valued semi-floating-gate recharged logic O Mirmotahari, Y Berg Proceedings. 34th International Symposium on Multiple-Valued Logic, 210-213, 2004 | 22 | 2004 |
| Multi-valued digital information retaining elements and memory devices P Lablans US Patent 7,397,690, 2008 | 20 | 2008 |
| A novel multiple-input multiple-valued semi-floating-gate latch O Mirmotahari, Y Berg 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings …, 2003 | 20 | 2003 |
| Rethinking learning in the digital age: Making the learning sciences count J Kay, R Luckin 13th International Conference of the Learning Sciences 3, 2018 | 16 | 2018 |
| Low-power high-speed rail-to-rail LCD output buffer with dual-path push–pull operation and quiescent current control D Marano, G Palumbo, S Pennisi Analog Integrated Circuits and Signal Processing 65, 289-298, 2010 | 15 | 2010 |
| Multi-state latches from n-state reversible inverters P Lablans US Patent 7,656,196, 2010 | 15 | 2010 |
| Binary to multiple-valued recharge converter for multiple-valued cmos logic Y Berg, S Aunet, Ø Næss, O Mirmotahari, M Høvin ECCTD’03-Euopean Conference on Circuit Theory and Design, Cracow, Poland …, 2003 | 15 | 2003 |
| Band pass pseudo floating-gate amplifier Y Berg, M Azadmehr, O Mirmotahari, S Aunet 2007 14th IEEE International Conference on Electronics, Circuits and Systems …, 2007 | 14 | 2007 |
| Difficulties learning computer architecture O Mirmotahari, C Holmboe, J Kaasbøll Proceedings of the 8th annual conference on Innovation and technology in …, 2003 | 14 | 2003 |
| A case-study of automated feedback assessment O Mirmotahari, Y Berg, S Gjessing, E Fremstad, C Damsa 2019 IEEE Global Engineering Education Conference (EDUCON), 1190-1197, 2019 | 13 | 2019 |
| Robust low-power CMOS precharge logic O Mirmotahari, Y Berg 2013 IEEE Faible Tension Faible Consommation, 1-4, 2013 | 13 | 2013 |
| Ultra low-voltage CMOS current mirrors Y Berg, O Mirmotahari Analog Integrated Circuits and Signal Processing 68, 219-232, 2011 | 13 | 2011 |
| Bidirectional front-end for piezoelectric resonator L Marchetti, Y Berg, O Mirmotahari, M Azadmehr 2016 IEEE 13th International Conference on Networking, Sensing, and Control …, 2016 | 12 | 2016 |
| Basic multiple-valued functions using recharge CMOS logic Y Berg, S Aunet, O Noess, O Mirmotahari Proceedings. 34th International Symposium on Multiple-Valued Logic, 346-351, 2004 | 12 | 2004 |
| Novel high-speed and ultra-low-voltage cmos nand and nor domino gates Y Berg, O Mirmotahari CENICS 2012: The Fifth International Conference on Advances in Circuits …, 2012 | 11 | 2012 |
Yngvar BergProfessor - Nanoelectronic System Group - Dept. of Informatics - University of Oslo - Norwayبريد إلكتروني تم التحقق منه على ifi.uio.no
