| SpinalFlow: an architecture and dataflow tailored for spiking neural networks S Narayanan, K Taht, R Balasubramonian, E Giacomin, PE Gaillardon 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 109 | 2020 |
| Gencache: Leveraging in-cache operators for efficient sequence alignment A Nag, CN Ramachandra, R Balasubramonian, R Stutsman, E Giacomin, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 76 | 2019 |
| OpenFPGA: An open-source framework for agile prototyping customizable FPGAs X Tang, E Giacomin, B Chauviere, A Alacchi, PE Gaillardon IEEE Micro 40 (4), 41-48, 2020 | 61 | 2020 |
| OpenFPGA: An opensource framework enabling rapid prototyping of customizable FPGAs X Tang, E Giacomin, A Alacchi, B Chauviere, PE Gaillardon 2019 29th International Conference on Field Programmable Logic and …, 2019 | 59 | 2019 |
| A robust digital RRAM-based convolutional block for low-power image processing and learning applications E Giacomin, T Greenberg-Toledo, S Kvatinsky, PE Gaillardon IEEE Transactions on Circuits and Systems I: Regular Papers 66 (2), 643-654, 2018 | 58 | 2018 |
| Wire-aware architecture and dataflow for CNN accelerators S Gudaparthi, S Narayanan, R Balasubramonian, E Giacomin, ... Proceedings of the 52nd annual ieee/acm international symposium on …, 2019 | 48 | 2019 |
| A predictive process design kit for three-independent-gate field-effect transistors G Gore, P Cadareanu, E Giacomin, PE Gaillardon 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 38 | 2019 |
| A study on switch block patterns for tileable FPGA routing architectures X Tang, E Giacomin, A Alacchi, PE Gaillardon 2019 International Conference on Field-Programmable Technology (ICFPT), 247-250, 2019 | 31 | 2019 |
| Differential power analysis mitigation technique using three-independent-gate field effect transistors E Giacomin, PE Gaillardon 2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018 | 23 | 2018 |
| FPGA-SPICE: A simulation-based architecture evaluation framework for FPGAs X Tang, E Giacomin, G De Micheli, PE Gaillardon IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (3), 637-650, 2018 | 22 | 2018 |
| Low-power multiplexer designs using three-independent-gate field effect transistors E Giacomin, JR Gonzalez, PE Gaillardon 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2017 | 20 | 2017 |
| Circuit designs of high-performance and low-power RRAM-based multiplexers based on 4T (ransistor) 1R (RAM) programming structure X Tang, E Giacomin, G De Micheli, PE Gaillardon IEEE Transactions on Circuits and Systems I: Regular Papers 64 (5), 1173-1186, 2016 | 20 | 2016 |
| Post-P&R performance and power analysis for RRAM-based FPGAs X Tang, E Giacomin, G De Micheli, PE Gaillardon IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (3 …, 2018 | 17 | 2018 |
| A RRAM-based FPGA for Energy-efficient Edge Computing X Tang, E Giacomin, P Cadareanu, G Gore, PE Gaillardon 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 144 …, 2020 | 12 | 2020 |
| A product engine for energy-efficient execution of binary neural networks using resistive memories J Vieira, E Giacomin, Y Qureshi, M Zapater, X Tang, S Kvatinsky, ... 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 11 | 2019 |
| Low latency SEU detection in FPGA CRAM with in-memory ECC checking A Alacchi, E Giacomin, S Temple, R Gauchi, M Wirthlin, PE Gaillardon IEEE Transactions on Circuits and Systems I: Regular Papers 70 (5), 2028-2036, 2023 | 10 | 2023 |
| A novel high-gain amplifier circuit using super-steep-subthreshold-slope field-effect transistors M Couriol, P Cadareanu, E Giacomin, PE Gaillardon 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration …, 2021 | 8 | 2021 |
| Digital RRAM-based convolutional block P Gaillardon, E Giacomin, J Vieira US Patent 11,450,385, 2022 | 7 | 2022 |
| Physical design considerations of one-level RRAM-based routing multiplexers X Tang, E Giacomin, G De Micheli, PE Gaillardon Proceedings of the 2017 ACM on International Symposium on Physical Design, 47-54, 2017 | 7 | 2017 |
| Smart-redundancy: An alternative SEU/SET mitigation method for FPGAs A Alacchi, E Giacomin, X Tang, PE Gaillardon 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 6 | 2021 |
Pierre - Emmanuel GAILLARDONProfessor, University of Utahبريد إلكتروني تم التحقق منه على utah.edu