| System and method for modeling, abstraction, and analysis of software F Ivancic, PN Ashar, M Ganai, A Gupta, Z Yang US Patent 7,346,486, 2008 | 300 | 2008 |
| Guarded evaluation: Pushing power management to logic synthesis/design V Tiwari, S Malik, P Ashar Proceedings of the 1995 international symposium on Low power design, 221-226, 1995 | 284 | 1995 |
| Technology mapping for lower power V Tiwari, P Ashar, S Malik Proceedings of the 30th international Design Automation Conference, 74-79, 1993 | 212 | 1993 |
| Sequential logic synthesis P Ashar, S Devadas, AR Newton Springer Science & Business Media, 1992 | 200 | 1992 |
| Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver MK Ganai, P Ashar, A Gupta, L Zhang, S Malik Proceedings of the 39th annual Design Automation Conference, 747-750, 2002 | 168 | 2002 |
| Efficient SAT-based bounded model checking for software verification F Ivančić, Z Yang, MK Ganai, A Gupta, P Ashar Theoretical Computer Science 404 (3), 256-274, 2008 | 167 | 2008 |
| F-Soft: Software Verification Platform F Ivančić, Z Yang, MK Ganai, A Gupta, I Shlyakhter, P Ashar Computer Aided Verification: 17th International Conference, CAV 2005 …, 2005 | 155 | 2005 |
| Scheduling techniques to enable power management J Monteiro, S Devadas, P Ashar, A Mauskar Proceedings of the 33rd annual Design Automation Conference, 349-352, 1996 | 154 | 1996 |
| SAT-based image computation with application in reachability analysis A Gupta, Z Yang, P Ashar, A Gupta International Conference on Formal Methods in Computer-Aided Design, 391-408, 2000 | 145* | 2000 |
| Fast functional simulation using branching programs P Ashar, S Malik Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 135 | 1995 |
| Accelerating Boolean satisfiability with configurable hardware P Zhong, M Martonosi, P Ashar, S Malik Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No …, 1998 | 121 | 1998 |
| Simulation vector generation from HDL descriptions for observability-enhanced statement coverage F Fallah, P Ashar, S Devadas Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 666-671, 1999 | 110 | 1999 |
| Efficient SAT-based unbounded symbolic model checking using circuit cofactoring MK Ganai, A Gupta, P Ashar IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 102 | 2004 |
| Content-based information retrieval architecture S Cadambi, J Kilian, P Ashar, ST Chakradhar US Patent 7,019,674, 2006 | 101 | 2006 |
| Iterative abstraction using SAT-based BMC with proof analysis A Gupta, M Ganai, Z Yang, P Ashar ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 100 | 2003 |
| Boolean satisfiability and equivalence checking using general binary decision diagrams P Ashar, A Ghosh, S Devadas Integration 13 (1), 1-16, 1992 | 96 | 1992 |
| Verification of scheduling in the presence of loops using uninterpreted symbolic simulation P Ashar, A Raghunathan, S Bhattacharya US Patent 7,383,166, 2008 | 82 | 2008 |
| Optimum and heuristic algorithms for an approach to finite state machine decomposition P Ashar, S Devadas, AR Newton IEEE transactions on computer-aided design of integrated circuits and …, 2002 | 77 | 2002 |
| Efficient breadth-first manipulation of binary decision diagrams P Ashar, M Cheong Proceedings of the 1994 IEEE/ACM international conference on computer-aided …, 1994 | 77 | 1994 |
| Using configurable computing to accelerate Boolean satisfiability P Zhong, M Martonosi, P Ashar, S Malik IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999 | 75 | 1999 |
